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RT8061A ? ds8061a-04 september 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. (top view) pin configurations ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. 3a, 1mhz, synchronous step-down converter general description the RT8061A is a high efficiency synchronous, step-down dc/dc converter. its input voltage range from 2.7v to 5.5v that provides an adjustable regulated output voltage from 0.6v to v in while delivering up to 3a of output current. the internal synchrono us low on resistance power switches increase efficiency and eliminate the need for an external schottky diode. the switching frequency is fixed internally at 1mhz. the 100% duty cycle provides low dropout operation, hence extending battery life in portable systems. current mode operation with internal compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the RT8061A is operated in pwm/psm mode to achieve high efficiency for a wide load range. the RT8061A is available in a wdfn-10l 3x3 package. applications z portable instruments z battery-powered equipment z notebook computers z distributed power systems z ip phones z digital cameras features z z z z z high efficiency : up to 95% z z z z z low r ds(on) internal switches : 69m /49m at v in = 5v z z z z z fixed frequency : 1mhz z z z z z no schottky diode required z z z z z 0.6v reference allows low output voltage z z z z z pwm/psm mode operation z z z z z low dropout operation : 100% duty cycle z z z z z ocp, uvp, ovp, otp z rohs compliant and halogen free wdfn-10l 3x3 nc lx en pgood pvin pvin svin fb nc lx 9 8 7 1 2 3 4 5 10 6 gnd 11 marking information 11 : product code ymdnn : date code 11 ym dnn package type qw : wdfn-10l 3x3 (w-type) RT8061A lead plating system z : eco (ecological element with halogen free and pb free)
RT8061A 2 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram functional pin description pin no. pin name pin function 1, 7 nc no internal connection. 2, 3 lx switch node. connection this pin to the inductor. 4 pgood power good indicator. this pin is an open drain logic output that is pulled to ground when the output voltage is less than 90% of the target output voltage. 5 en enable control. pull high to turn on. do not float. 6 fb feedback. this pin receives the feedback voltage from a resistive voltage divider connected across the output. 8 svin signal input. decouple this pin to gnd with at least 1 f ceramic cap. 9, 10 pvin power input. decouple this pin to gnd with at least 4.7 f ceramic cap. 11 (exposed pad) gnd the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. typical application circuit pgood driver nisen control logic zero current 0.72v 0.54v 0.4v oc limit isen slope com osc pgood output clamp en 0.6v int-ss por otp v ref en fb pvin svin en lx ov uv pgood 5 en RT8061A lx 2, 3 fb 6 l out v out gnd 11 (exposed pad) r fb1 r fb2 c out chip enable c in c1 r1 pvin svin pgood 9, 10 8 4 v in pgood c ff
RT8061A 3 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (v in = 3.3v, t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) z supply input v oltage, pvin, svin -------------------------------------------------------------------------------- ? 0.3v to 6.5v z lx pin v oltage --------------------------------------------------------------------------------------------------------- (v in + 0.3v) to 6.8v z other i/o pin voltage ------------------------------------------------------------------------------------------------ ? 0.3v to 6.5v z power dissipation, p d @ t a = 25 c wdnf-10l 3x3 -------------------------------------------------------------------------------------------------------- 1.429w z package thermal resistance (note 2) wdfn-10l 3x3, ja -------------------------------------------------------------------------------------------------- 70 c/w wdfn-10l 3x3 jc -------------------------------------------------------------------------------------------------- 8.2 c/w z junction temperature ------------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ----------------------------------------------------------------------------------------- 2kv recommended operating conditions (note 4) z supply input v oltage, pvin, svin -------------------------------------------------------------------------------- 2.7v to 5.5v z junction temperature range --------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max unit feedback reference voltage v ref 0.594 0.6 0.606 v feedback leakage current i fb -- 0.1 0.4 a active , v fb = 0.7v, not switching -- 110 140 dc bias current shutdown -- -- 1 a output voltage line regulation v in = 2.7v to 5.5v i out = 0a -- 0.3 -- %/v output voltage load regulation i out = 0a to 3a ? 1 -- 1 % switch leakage current v en = 0a -- -- 1 a switching frequency 0.8 1 1.2 mhz switch on resistance, high r ds(on)_p v in = 5v -- 69 -- m switch on resistance, low r ds(on)_n v in = 5v -- 49 -- m pmos current limit (latch-off) i lim 4 -- -- a v in rising 2.2 2.4 2.6 under voltage lockout threshold v uvlo v in falling 2 2.2 2.4 v logic-high v ih 1.6 -- -- en threshold voltage logic-low v il -- -- 0.4 v en pull low resistance -- 500 -- k
RT8061A 4 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit over temperature protection (latch-off) t sd -- 150 -- c soft-start time t ss 500 -- -- s v out discharge resistance -- 100 -- v out over voltage protection (latch-off, delay time = 10 s) 115 120 130 % v out under voltage lockout threshold (latch-off) 57 66 75 % power good measured fb, with respect to v ref 85 90 -- % power good hysteresis -- 5 -- % note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8061A 5 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics current limit vs. temperature 3.0 3.8 4.6 5.4 6.2 7.0 -50 -25 0 25 50 75 100 125 temperature ( c) current limit (a) v out = 1.05v v in = 5v v in = 3.3v current limit vs. input voltage 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) current limit (a) v out = 1.05v efficiency vs. load current 70 75 80 85 90 95 100 00.511.522.53 load current (a) efficiency (%) v out = 1.05v v in = 5v v in = 3.3v efficiency vs. load current 86 88 90 92 94 96 98 100 00.511.522.53 load current (a) efficiency (%) v out = 3.3v v in = 5v v in = 4.2v efficiency vs. load current 80 82 84 86 88 90 92 94 96 98 100 00.511.522.53 load current (a) efficiency (%) v out = 1.8v v in = 5v v in = 3.3v output voltage vs. output current 1.780 1.788 1.796 1.804 1.812 1.820 0 0.6 1.2 1.8 2.4 3 output current (a) output voltage (v) v out = 1.8v v in = 5v v in = 3.3v
RT8061A 6 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. load transient response time (50 s/div) v in = 5v, v out = 1.8v, i out = 1.5a to 3a v out (50mv/div) i out (2a/div) over voltage protection time (10 s/div) v in = 5v, v out = 1.8v, i out = 1a v lx (2v/div) v out (1v/div) switching time (500ns/div) v out (5mv/div) i lx (2a/div) v in = 5v, v out = 1.8v, i out = 3a v lx (500mv/div) switching time (500ns/div) v out (5mv/div) v lx (500mv/div) i lx (1a/div) v in = 5v, v out = 1.8v, i out = 1.5a load transient response time (50 s/div) v in = 5v, v out = 1.8v, i out = 0.5a to 3a v out (50mv/div) i out (2a/div) r ds(on) vs. temperature 35 46 57 68 79 90 -50 -25 0 25 50 75 100 125 temperature ( c) r ds(on) (m ) v in = 5v p-mosfet n-mosfet
RT8061A 7 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. under voltage protection time (5 s/div) v in = 5v, v out = 1.8v v lx (2v/div) v out (1v/div) over current protection time (2.5 s/div) v in = 5v, v out = 1.8v v lx (5v/div) v out (1v/div) i lx (5a/div) power off from v in v in (2v/div) v out (1v/div) i lx (2a/div) time (2.5ms/div) v out = 1.8v, i out = 3a power off from en time (40 s/div) v en (5v/div) v out (1v/div) i lx (2a/div) v in = 5v, v out = 1.8v, i out = 3a power on from en time (200 s/div) v en (5v/div) v out (1v/div) i lx (2a/div) v in = 5v, v out = 1.8v, i out = 3a power on from v in time (2.5ms/div) v out = 1.8v, i out = 3a v in (2v/div) v out (1v/div) i lx (2a/div)
RT8061A 8 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. fb gnd r1 v out r2 application information the RT8061A is a single-phase buck pwm converter. it provides single feedback loop, current mode control with fast transient response. an internal 0.6v reference allows the output voltage to be precisely regulated for low output voltage applications. a fixed switching frequency (1mhz) oscillator and internal compensation are integrated to minimize external component count. protection features include over current protection, under voltage protection, over voltage protection and over temperature protection. pwm operation the RT8061A utilizes dem control to improve light load efficiency. depending on the load current, the controller automatically operates in diode-emulation mode (dem) or in continuous conduction mode (ccm) with fixed- frequency pwm. at light load condition, the RT8061A automatically operates in diode-emulation mode to reduce switching frequency and improve efficiency. as the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point where its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low side mosfet allows only partial negative current to flow when the inductor freewheeling current reaches negative. as the load current further decreases, it takes longer and longer to discharge the output capacitor to the level that that requires the next ugate ? on ? cycle. in contrast, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. the controller will then operate in continuous conduction mode with 1mhz fixed pwm switching frequency. output voltage setting connect a resistive voltage divider at the fb between v out and gnd to adjust the output voltage. the output voltage is set according to the following equation : where v fb is 0.6v (typ.). ( ) out in out sw load(max) in vvv l = fliri v ? figure 1 . setting v out with a voltage divider chip enable and disable the en pin allows for power sequencing between the controller bias voltage and another voltage rail. the RT8061A remains in shutdown if the en pin is lower than 400mv. when the en pin rises above the v en trip point, the RT8061A begins a new initialization and soft-start cycle. internal soft-start the RT8061A provides an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. the soft-start (ss) automatically begins once the chip is enabled. during soft- start, the internal soft-start capacitor becomes charged and generates a linear ramping up voltage across the capacitor. this voltage clamps the voltage at the fb pin, causing pwm pulse width to increase slowly and in turn reduce the output surge current. the internal 0.6v reference takes over the loop control once the internal ramping-up voltage becomes higher than 0.6v. uvlo protection the RT8061A has input under voltage lockout protection (uvlo). if the input voltage exceeds the uvlo rising threshold voltage (2.4v typ.), the converter resets and prepares the pwm for operation. if the input voltage falls below the uvlo falling threshold voltage during normal operation, the device will stop switching. the uvlo rising and falling threshold voltage has a hysteresis to prevent noise-caused reset. inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as shown below : ?? ?? ?? out fb r1 v= v 1+ r2
RT8061A 9 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. where lir is the ratio of the peak-to-peak ripple current to the average inductor current. find a low loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ) : the calculation above serves as a general reference. to further improve transient response, the output inductor can be further reduced. this relation should be considered along with the selection of the output capacitor. input capacitor selection high quality ceramic input decoupling capacitor, such as x5r or x7r, with values greater than 20 f are recommended for the input capacitor. the x5r and x7r ceramic capacitors are usually selected for power regulator capacitors because the dielectric material has less capacitance variation and more temperature stability. voltage rating and current rating are the key parameters when selecting an input capacitor. generally, selecting an input capacitor with voltage rating 1.5 times greater than the maximum input voltage is a conservatively safe design. the input capacitor is used to supply the input rms current, which can be approximately calculated using the following equation : ?? = ? ?? ?? out out in_rms load in in vv ii 1 vv the next step is selecting a proper capacitor for rms current rating. one good design is using more than one capacitor with low equivalent series resistance (esr) in parallel to form a capacitor bank. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be approximately calculated using the following equation : = out(max) in in sw i0.25 v cf for example, if i out(max) = 3a, c in = 20 f, f sw = 1mhz, the input voltage ripple will be 37.5mv. ?? = + ?? ?? p-p load(max) out sw 1 v lir i esr 8c f when load transient occurs, the output capacitor supplies the load current before the controller can respond. therefore, the esr will dominate the output voltage sag during load transient. the output voltage undershoot (v sag ) can be calculated by the following equation : = sag load viesr for a given output voltage sag specification, the esr value can be determined. another parameter that has influence on the output voltage sag is the equivalent series inductance (esl). the rapid change in load current results in di/dt during transient. therefore, the esl contributes to part of the voltage sag. using a capacitor with low esl can obtain better transient performance. generally, using several capacitors connected in parallel can have better transient performance than using a single capacitor for the same total esr. unlike the electrolytic capacitor, the ceramic capacitor has relatively low esr and can reduce the voltage deviation during load transient. however, the ceramic capacitor can only provide low capacitance value. therefore, use a mixed combination of electrolytic capacitor and ceramic capacitor to obtain better transient performance. power good output (pgood) pgood is an open-drain type output and requires a pull- up resistor. pgood is actively held low in soft-start, standby, and shutdown. it is released when the output voltage rises above 90% of nominal regulation point. the pgood signal goes low if the output is turned off or is 10% below its nominal regulation point. ?? + ?? ?? peak load(max) load(max) lir i = i i 2 output capacitor selection the output capacitor and the inductor form a low pass filter in the buck topology. in steady state condition, the ripple current flowing into/out of the capacitor results in ripple voltage. the output voltage ripple (v p-p ) can be calculated by the following equation :
RT8061A 10 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. under voltage protection (uvp) the output voltage can be continuously monitored for under voltage. when under voltage protection is enabled, both ugate and lgate gate drivers will be forced low if the output is less than 66% of its set voltage threshold. the uvp will be ignored for at least 3ms (typ.) after start up or a rising edge on the en threshold. toggle en threshold or cycle v in to reset the uvp fault latch and restart the controller. over voltage protection (ovp) the RT8061A is latched once ovp is triggered and can only be released by toggling en threshold or cycling v in . there is a 10 s delay built into the over voltage protection circuit to prevent false transition. over current protection (ocp) the RT8061A provides over current protection by detecting high side mosfet peak inductor current. if the sensed peak inductor current remains over 4a (typ) for 5 clock cycles, ocp will be triggered. when ocp trips, the RT8061A will shut down and enter latch-off mode to stop the energy transfer to the load. in latch-off mode, the RT8061A can only be reset by en or v in . thermal shutdown (otp) the device implements internal thermal shutdown when the junction temperature exceeds 150 c. when the otp function is triggered, the RT8061A shuts down and enters latch-off mode. in latch-off mode, the RT8061A can be reset by en or v in . thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn-10l 3x3 packages, the thermal resistance, ja , is 70 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (70 c/w) = 1.429w for wdfn-10l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 2 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 2. derating curve of maximum power dissipation 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8061A 11 ds8061a-04 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations layout is very important in high frequency switching converter design. the pcb can radiate excessive noise and contribute to converter instability with improper layout. certain points must be considered before starting a layout using the RT8061A. ` make the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (v in and gnd). ` lx node encounters high frequency voltage swings so it should be kept in a small area. keep sensitive components away from the lx node to prevent stray capacitive noise pick-up. ` ensure all feedback network connections are short and direct. place the feedback network as close to the chip as possible. ` the gnd pin and exposed pad should be connected to a strong ground plane for heat sinking and noise protection. ` an example of pcb layout guide is shown in figure 3. for reference. figure 3. pcb layout guide nc lx en pgood pvin pvin svin fb nc lx 9 8 7 1 2 3 4 5 10 6 gnd 11 r1 r2 c in2 c in1 r en r pgood v in v out c out gnd v out input capacitor must be placed as close to the ic as possible. lx should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the output capacitor must be placed near the ic. the voltage divider must be connected as close to the device as possible.
RT8061A 12 ds8061a-04 september 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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